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A Reprogrammable Computing Platform for JPEG 2000 and H.264 SHD Video Coding

Publication typeConference paper
Year of publication2010
AuthorsGiuseppe Baruffa, Federico Fiorucci, Fabrizio Frescura, Paolo Micanti, Ludovico Verducci, and Barbara Villarini
TitleA Reprogrammable Computing Platform for JPEG 2000 and H.264 SHD Video Coding
Conference name8th IEEE Workshop on Embedded Systems for Real-time Multimedia (Estimedia 2010)
Volume
Issue
Pages107–113
Editor
PublisherIEEE
DateOctober 2010
PlaceScottsdale, AZ, USA
ISSN number
ISBN number9781424490844
Key words
AbstractIn this paper we present the architecture of a DSP/FPGA based hardware platform, conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD resolutions, have been simulated and their performance found on the embedded processing cores. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability.
URLhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5666990
DOIhttp://dx.doi.org/10.1109/ESTMED.2010.5666990
Other information
Paper
Last update: 2015-10-12, 16:44:51