Publications

Copyright information: personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the publisher.

A multi-standard reconfigurable Viterbi decoder using embedded FPGA blocks

Publication type	Conference paper
Year of publication	2006
Authors	Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, and Andrea Scorzoni
Title	A multi-standard reconfigurable Viterbi decoder using embedded FPGA blocks
Conference name	9th EUROMICRO Conference on Digital System Design (DSD 2006)
Volume
Issue
Pages	146–151
Editor	Venki Muthukumar
Publisher
Date	August 2006
Place	Cavtat near Dubrovnik, Croatia
ISSN number
ISBN number	0-7695-2609-8
Key words
Abstract	This paper presents a Viterbi Decoder (VD) architecture for a reprogrammable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a Software Defined Radio (SDR) mobile transceiver, reconfigurable on user request and capable to provide agility in choosing between different standards. UMTS and GPRS standards decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of reconfigurability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA, such as to provide a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupation of 45%, due to the efficient resource reuse.
URL	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1690033
DOI	http://dx.doi.org/10.1109/DSD.2006.12
Other information
Paper	(portable document format, 6459553 Bytes)