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A reconfigurable channel codec coprocessor for software radio multimedia applications
| Publication type | Conference paper |
|---|---|
| Year of publication | 2003 |
| Authors | Andrea Pacifici, Caterina Vendetti, Fabrizio Frescura, and Saverio Cacopardi |
| Title | A reconfigurable channel codec coprocessor for software radio multimedia applications |
| Conference name | 2003 International Symposium on Circuits and Systems (ISCAS 03) |
| Volume | 2 |
| Issue | |
| Pages | 41–44 |
| Editor | |
| Publisher | IEEE |
| Date | May 2003 |
| Place | Bangkok, Thailand |
| ISSN number | |
| ISBN number | 0-7803-7761-3 |
| Key words | software radio, dsp, coprocessor |
| Abstract | This paper describes a coprocessor architecture for channel coding and decoding in software radio high bit rate applications. The proposed approach has been implemented in VHDL code. After a brief introduction about main target applications, and the motivation for the proposed architecture, we show the high level device layout, dwelling upon every single entity. Coprocessor functional behaviour has been analyzed by a Visual C++ simulator designed to this aim; in this document we show some of the most significant simulation results. |
| URL | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1205881 |
| DOI | http://dx.doi.org/10.1109/ISCAS.2003.1205881 |
| Other information | |
| Paper |