%0 Conference Paper
%B 8th IEEE Workshop on Embedded Systems for Real-time Multimedia (Estimedia 2010)
%D 2010
%T A Reprogrammable Computing Platform for JPEG 2000 and H.264 SHD Video Coding
%A Baruffa, Giuseppe
%A Fiorucci, Federico
%A Frescura, Fabrizio
%A Micanti, Paolo
%A Verducci, Ludovico
%A Villarini, Barbara
%C Scottsdale, AZ
%E IEEE
%K FPGA, DSP, JPEG 2000, H.264, JPWL, video processing
%M 11697879
%P 107-113
%U http://www.estimedia.org/
%X In this paper we present the architecture of a DSP/FPGA based hardware platform, conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD resolutions, have been simulated and their performance found on the embedded processing cores. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability.
%8 October 2010
%@ 978-1-4244-9084-4